1. Field of the Invention
The present invention relates to a field effect transistor with an improved gate overlap drain structure and a method of manufacturing the same by utilizing a laser beam irradiation technique as well as a liquid crystal display using the same and a method of manufacturing the same.
All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will, hereby, be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
2. Description of the Related Art
In recent years, shrinkage of the semiconductor device causes shortening a gate width of a field effect transistor. The shortened gate width may cause short channel effects and hot carrier injections, thereby resulting in deterioration of reliability of the field effect transistor. The short channel effects and the hot carrier injections may cause an extensively high field in the vicinity of the drain region of the transistor. In order to avoid the above undesired problems, it is effective to reduce or relax an extensively high field in the vicinity of the drain region of the transistor. In order to reduce or relax an extensively high field, a lightly doped drain (LLD) structure is effective, which has been known in the art, to which the present invention pertains. In accordance with the lightly doped drain (LLD) structure, off-set gate layers having lower impurity concentration are selectively formed in selected substrate regions between source/drain regions and a channel region under a gate electrode. The off-set gate layers contribute to relax undesired extensively high fields in the selected substrate regions between the source/drain regions and the channel region under the gate electrode. The off-set gate layers thus contribute to increase the withstand voltages, for example, a punch-through voltage and a hot carrier withstand voltage.
A method of forming a typical example of a conventional lightly doped drain structure will be described with reference to FIGS. 1A through 1C.
As shown in FIG. 1A, an isolation oxide film 14 is selectively formed over a silicon substrate 13 by a local oxidation of silicon method, thereby to define a field region which is surrounded by the isolation oxide film 14. A gate oxide film 4 is formed on the field region by a thermal oxidation. A polysilicon film is then deposited by a low pressure chemical vapor deposition method over the gate oxide film 4 and the isolation oxide film 14. A photo-lithography and a subsequent dry etching process are then carried out to form a gate electrode 5. A first ion-implantation is then carried out at a low impurity concentration by use of the gate electrode 5 and the isolation oxide film 14 as masks for subsequent anneal under predetermined conditions to form low impurity concentration regions 16.
As shown in FIG. 1B, a silicon oxide film is deposited by a low pressure chemical vapor deposition method over the gate electrode 5 and the isolation oxide film 14 as well as the low impurity concentration regions 16. An anisotropic etching such as a dry etching is then carried out to etch-back the silicon oxide film, thereby to selectively form side wall oxide films 17 on opposite side walls of the gate electrode 5.
As shown in FIG. 1C, a second ion-implantation is carried out at a high impurity concentration by use of the gate electrode 5, the side wall oxide films 17 and the isolation oxide film 14 as masks for subsequent anneal under predetermined conditions to form high impurity concentration regions 18, while the low impurity concentration regions 16 remain only under the side wall oxide films 17, wherein boundaries between the high impurity concentration regions 18 and the low impurity concentration regions 16 are self-aligned to the outside edges of the side wall oxide films 17. The high impurity concentration regions 18 serve as source and drain regions, while the remaining low impurity concentration regions 16 under the side wall oxide films 17 serve as the off-set gate layers.
The above lightly doped drain structure is, indeed, effective to relax the expensively high field concentration. Further high degree of shrinkage of the semiconductor device causes a further high degree of shortening the gate width which defines the channel width, namely of shortening the channel width. Increase in the degree of shortening the channel width may cause an undesired phenomenon that hot carriers generated in the vicinity of the drain region are trapped into side regions of the gate oxide film in the vicinity of the lightly doped drain regions or the low impurity concentration regions 16. The trapped hot carriers may cause an undesired inversion in the conductivity type of the lightly doped drain regions 16. The inversion in the conductivity type of the lightly doped drain regions 16 may cause an undesired variation in threshold voltage of the transistor and also an undesired drop of the punch-through withstand voltage.
In the meantime, it has been known in the art, to which the present invention pertains, a thin film transistor as typical one of the field effect transistors is used as a switching device for a liquid crystal display. In accordance with a basic structure of a polycrystal silicon thin film transistor used as a pixel switching transistor in the liquid crystal display, the lightly doped drain structure is effective to suppress or reduce a leakage of current, which may be a dark current. This lightly doped drain structure and the channel region of the polycrystal silicon thin film transistor have an disadvantage in possible increase in leakage of current or dark current upon incidence of light into the channel region, namely an off-leak current upon incidence of light into the channel region.
In order to reduce such undesired off-leak current upon incidence of light into the channel region, a pair of top and bottom light shielding layers is provided, wherein the top light shielding layer overlies the transistor, while the bottom light shielding layer underlies the transistor. As described above, in accordance with the lightly doped drain structure, the low impurity concentration regions are not covered by the gate electrode. This structure allows a light reflected by respective layers in an active matrix substrate of the display to become incident into the low impurity concentration regions, even the top and bottom optical shielding layers are provided. Namely, it is difficult to avoid the undesirable leakage of light or possible incidence of light into the low impurity concentration regions unless the low impurity concentration regions are completely covered by the gate electrode. This problem will be remarkable in a light valve active matrix liquid crystal display for liquid crystal light projection.
In order to have attempted to solve the above problems with the undesired possible trap of the hot carriers into the gate oxide film and with the undesired possible light incidence into the low impurity concentration regions, a gate-overlap-drain structure was proposed, wherein laminations of a gate insulation film and a gate electrode extend over the lightly doped drain structure, or over the low impurity concentration regions. This gate-overlap-drain structure is disclosed in Japanese laid-open patent publications Nos. 8-153875 and 8-222736. This gate-overlap-drain structure will be described.
FIGS. 2A through 2D are fragmentary cross sectional elevation views of field effect transistors in sequential steps involved in a typical example of a conventional method of forming a gate-overlap-drain structure.
As shown in FIG. 2A, an isolation oxide film 14 is selectively formed over a silicon substrate 13 by a local oxidation of silicon method, thereby to define a field region which is surrounded by the isolation oxide film 14. A gate oxide film 4 is formed on the field region by a thermal oxidation. A resist pattern 10 is selectively formed in the field region, wherein the resist pattern 10 has a smaller size than an intended size of a gate electrode to be formed in later. A first ion-implantation is then carried out at a low impurity concentration by use of the resist pattern 10 and the isolation oxide film 14 as masks for subsequent anneal under predetermined conditions to form low impurity concentration regions 16. After the first ion-implantation is completed, then the used resist pattern 10 is removed.
As shown in FIG. 2B, a polysilicon film is then deposited by a low pressure chemical vapor deposition method over the gate oxide film 4 and the isolation oxide film 14. A photo-lithography and a subsequent dry etching process are then carried out to form a gate electrode 5 which has a larger size than the above-described resist pattern 10 which was already been removed, so that side regions of the gate electrode 5 overlap inside regions of the low impurity concentration regions 16.
As shown in FIG. 2C, a second ion-implantation is carried out at a high impurity concentration by use of the gate electrode 5 and the isolation oxide film 14 as masks for subsequent anneal under predetermined conditions to form high impurity concentration regions 18, while the low impurity concentration regions 16 remain only under the overlap side regions of the gate electrode 5, wherein boundaries between the high impurity concentration regions 18 and the low impurity concentration regions 16 are self-aligned to the outside edges of the gate electrode 5. The high impurity concentration regions 18 serve as source and drain regions, while the remaining low impurity concentration regions 16 under the side regions of the gate electrode 5 serve as the off-set gate layers. The side regions of the gate electrode 5 overlap the remaining low impurity concentration regions 16, thereby forming a gate-overlap-drain structure.
As shown in FIG. 2D, an inter-layer insulator 6 is deposited over the gate electrode 5, the gate oxide film 4 and the isolation oxide film 14. Contact holes are selectively formed in the inter-layer insulator 6 and over the high impurity concentration regions 18 serving as the source and drain regions. Source and drain electrodes 7 are selectively formed within the contact holes and over the inter-layer insulator 6, so that the source and drain electrodes 7 are in contact with the high impurity concentration regions 18 serving as the source and drain regions, thereby forming a field effect transistor including a gate-overlap-drain structure.
FIGS. 3A through 3D are fragmentary cross sectional elevation views of field effect transistors in sequential steps involved in another typical example of a conventional method of forming another gate-overlap-drain structure. This conventional technique is disclosed in Japanese laid-open patent publication No. 8-153875.
As shown in FIG. 3A, an isolation oxide film 14 is selectively formed over a silicon substrate 13 by a local oxidation of silicon method, thereby to define a field region which is surrounded by the isolation oxide film 14. A gate oxide film 4 is formed on the field region by a thermal oxidation. A polysilicon film is then deposited by a low pressure chemical vapor deposition method over the gate oxide film 4 and the isolation oxide film 14. A photo-lithography and a subsequent dry etching process are then carried out to form a gate electrode 5. A first ion-implantation is then carried out at a low impurity concentration by use of the gate electrode 5 and the isolation oxide film 14 as masks for subsequent anneal under predetermined conditions to form low impurity concentration regions 16.
As shown in FIG. 3B, a silicon-based film is entirely formed over the gate electrode 5 and the isolation oxide film 14 as well as the low impurity concentration regions 16. An anisotropic etching is then carried out to etch-back the silicon oxide film, thereby to selectively form side wall conductive films 19 on opposite side walls of the gate electrode 5. The side wall silicon-based films 19 are electrically conductive, for which reason the side wall conductive films 19 serve as part of the gate electrode in cooperation with the gate electrode 5.
As shown in FIG. 3C, a second ion-implantation is carried out at a high impurity concentration by use of the gate electrode 5, the side wall conductive films 19 and the isolation oxide film 14 as masks for subsequent anneal under predetermined conditions to form high impurity concentration regions 18, while the low impurity concentration regions 16 remain only under the side wall conductive films 19, wherein boundaries between the high impurity concentration regions 18 and the low impurity concentration regions 16 are self-aligned to boundaries between the side wall conductive films 19 and the gate electrode 5. The high impurity concentration regions 18 serve as source and drain regions, while the remaining low impurity concentration regions 16 under the side wall conductive films 19 serve as the off-set gate layers, thereby forming a gate-overlap-drain structure.
As shown in FIG. 3D, an inter-layer insulator 6 is deposited over the gate electrode 5, the side wall conductive films 19, the gate oxide film 4 and the isolation oxide film 14. Contact holes are selectively formed in the inter-layer insulator 6 and over the high impurity concentration regions 18 serving as the source and drain regions. Source and drain electrodes 7 are selectively formed within the contact holes and over the inter-layer insulator 6, so that the source and drain electrodes 7 are in contact with the high impurity concentration regions 18 serving as the source and drain regions, thereby forming a field effect transistor including a gate-overlap-drain structure.
In accordance with the above described conventional gate-overlap-drain structure, the side regions of the gate electrode overlap the lightly doped drain regions. This conventional gate-overlap-drain structure may prevent the above-described undesired influence of the hot carriers generated in the vicinity of the drain region. Further, the lightly doped drain regions are covered by the side regions of the gate electrode, wherein the side regions of the gate electrode serve as light shielding regions and improves a light-shieldability. Namely, the conventional gate-overlap-drain structure reduces the above problem with the light leakage.
The above-described conventional method for forming the conventional gate-overlap-drain structure, however, need at least two ion-implantation processes and further additional processes for forming the lightly doped drain regions under the side regions of the gate electrode. This results in complicated necessary processes for forming the conventional gate-overlap-drain structure.
Further, the anneal is carried out after the impurity has been selectively implanted, wherein the anneal reduces or relaxes an abruptness of the impurity concentration profile. This abruptness of the impurity concentration profile may cause an expensive highly field concentration, for which reason the reduction or the relaxation of the abruptness of the impurity concentration profile is effective to reduce or relax the expensive highly field concentration. FIG. 4 is a diagram of an impurity concentration profile across the channel region, the low impurity concentration region and the high impurity concentration region of the field effect transistor having the gate-overlap drain structure. As shown in FIG. 4, the impurity concentration profile includes two step-like variations in the impurity concentration at respective boundaries between the channel region and the low impurity concentration region and between the low impurity concentration region and the high impurity concentration region. Lager variation in the impurity concentration may cause a high field concentration. This impurity concentration profile with the two step-like variations makes it difficult to achieve a sufficient relaxation of the field concentration.
Furthermore, the above impurity concentration profile includes the abrupt step-like variation in impurity concentration at the boundary between the low impurity concentration region and the high impurity concentration region. This abrupt step-like variation in impurity concentration causes an undesirable abrupt and large variation in energy level at the boundary between the low impurity concentration region and the high impurity concentration region. Such abrupt and large variation in energy level promotes an undesired carrier trap, and a carrier re-combination, resulting in a shortened carrier life time.
In the above circumstances, the development of a novel field effect transistor free from the above problems is desirable.